Citaat | Parket bij de Hoge Raad 24 september 2021

Onder 5 Parket bij de Hoge Raad 24 september 2021

Een alinea uit Parket bij de Hoge Raad 24 september 2021, ECLI:NL:PHR:2021:847.

Overall, there is a need to look at the performance of the two configurations. However, it is not clear so far whether BRD is compatible with frame stealing for signalling, and the dynamic rate adaptation of the vocoder. It might well be that a TFCI is needed to indicate the s[p]eech rate and the presence of signalling, making the configuration 2 TFCI bits+ 2TPC bits+ 0 pilot the only viable option for support of EVRC. There would be no pilot bit and the SIR estimation would rely on the 2 bits TPC + 2bits TFCI. This would therefore lead to the introduction of a slot structure for SF=256 consisting of 16 bits for the DPDCH and 4 bits for the DPCCH with 2 bits TPC + 2bits TFCI + 0 bits Pilot. Other slot structures would be possible for that same SF and other SF, but would not be expected to support EVRC ultimately. Our recommendation is therefore to introduce such a slot structure in 25.211.”

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