Onder 2.4. Rechtbank Den Haag 30 november 2016

[0032] In the preferred embodiment, each FET of a primitive has its gate terminal coupled to an address line 642. There are therefore a number of address lines "N" in an address bus 640, 650 that is equal to the number of drop generators (and FETs) in each of the primitives shown (602, 604, 606, 608, 610, 612, 614, 615, 616, 618, 620, and 622). The address lines to the gates of the FETs of one set of primitives shown (602, 604, 606, 608, 610, 612) are electrically isolated from the gates of the FETs of the other set of primitives shown (614, 615, 616, 618, 620, and 622). (In an alternate embodiment, the two sets of address lines may be indirectly or directly coupled together.) The FETs in any set of primitives will not fire if those FETs are deactivated by their corresponding primitive control lines, depicted in FIG. 6A as the "P" lines 690. The address lines are therefore effectively multiplexed to reduce the number of address lines needed to control numerous transistors in several primitives while allowing for individual selectability (addressability) of the drop generators. The only exception to this would be if one or more truncated primitives P (with less than N drop generators) is utilized. During a printing operation, the printing system cycles through the address lines such that only one of the address lines A1 through AN is activated at a time. (See FIG. 6B.) Thus, within a primitive, only one drop generator can be activated at a time. However, all of the drop generators in the various primitives associated with a particular address can be fired simultaneously.

$ curl -s https://bron.page/api/v1/blobs/3d07ff3019757217b59383160e5bf39b464e9add3532f4826553c7971e2b7f84 | shasum -a 256