Onder 2.3. Rechtbank Den Haag 30 november 2016

[0040] A data transistor 136, a first address transistor 138 and a second address transistor 140 include drain-source paths that are electrically coupled in parallel. The parallel combination of data transistor 136, first address transistor 138 and second address transistor 140 is electrically coupled between the drain-source path of select transistor 130 and reference line 122. The serial circuit including select transistor 130 coupled to the parallel combination of data transistor 136, first address transistor 138 and second address transistor 140 is electrically coupled across node capacitance 126 of drive switch 172. The gate of data transistor 136 is electrically coupled to data line 142 that receives data signals ~DATA. The gate of first address transistor 138 is electrically coupled to an address line 144 that receives address signals ~ADDRESS1 and the gate of second address transistor 140 is electrically coupled to a second address line 146 that receives address signals ~ADDRESS2. The data signals ~DATA and address signals ~ADDRESS1 and ~ADDRESS2 are active when low as indicated by the tilda (~) at the beginning of the signal name. The node capacitance 126, precharge transistor 128, select transistor 130, data transistor 136 and address transistors 138 and 140 form a memory cell.

$ curl -s https://bron.page/api/v1/blobs/3d07ff3019757217b59383160e5bf39b464e9add3532f4826553c7971e2b7f84 | shasum -a 256